1. Field of the Invention
This invention relates to a fabrication method for an integrated circuit. More particularly, the invention relates to a fabrication method for an integrated circuit comprising a shallow trench isolation (STI) structure.
2. Description of the Related Art
In the fabrication of an integrated circuit comprising a shallow trench isolation structure, the oxide layer filling the shallow trench is damaged and forms a recess at the top edge corner of the trench during the removal of the pad oxide layer on the active region. The polysilicon, during its formation to become a gate, fills the recess. The top edge corner of the shallow trench isolation structure, as a result, is covered by the polysilicon, in which a local intensified field is induced, causing the transistor to have a lower threshold voltage in the area next to the shallow trench isolation structure and leading to an increase of the sub-threshold leakage of the transistor. As the line-width of an integrated circuit continues to be reduced, the effect of the local intensified field on the threshold voltage of a transistor becomes more significant. Since this phenomenon is opposite to the narrow-width-effect in which the threshold voltage increases with a reduction of the line width, it is therefore known as the inverse-narrow-width-effect.
In the conventional approach to reduce the inverse-narrow-width-effect. boron ions are implanted in the inner wall of the shallow trench to form a boron-doped region in the substrate along the shallow trench. The boron implantation is conducted after the formation of the trench and before the filling of the shallow trench with the oxide layer. The influence on the threshold voltage of a transistor by the local intensified field, because the top edge corner of the isolation structure is covered by polysilicon, is hence prevented. The boron doped region, formed according to the conventional approach, is distributed throughout the entire shallow trench sidewall and the substrate at the bottom of the trench. As a result, the P-N junction, formed by the connection of the boron-doped region and the source/drain region of the transistor, is in contact with the substrate. When the transistor is operating, the voltage applied to the transistor causes the P-N junction to generate a very high junction leakage in the substrate, seriously deteriorating the quality of the transistor. Especially in the dynamic random access memory (DRAM) cell structure, the junction leakage and the sub-threshold leakage due to the inverse-narrow-width-effect induce a serious drainage of the charge stored in the memory cell and greatly increase the frequency of the refresh cycle.